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uart_tx
FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)
- 2015-11-11 13:26:49下载
- 积分：1
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CORDIC算法的vhdl实现，包含一个说明文件
cordic算法的vhdl实现，内附有文档说明-cordic algorithm vhdl realized, a document containing a note
- 2022-01-26 06:23:45下载
- 积分：1
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DS1820
DS18B20温度传感器，用verilog语言实现(DS18B20 temperature sensor, with the verilog language)
- 2020-11-01 21:29:55下载
- 积分：1
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FPGA-root-operation
本文分析比较了实现开方运算的牛顿一莱福森算法、逐次逼近算法、非冗余开方算法种算法,并给出了基于的开方器的实现方法(Root operation FPGA-based implementation.pdf)
- 2012-11-04 01:44:02下载
- 积分：1
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四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL...
四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
- 2023-08-13 03:20:02下载
- 积分：1
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rc-evga-indtube
evga-indtube.h - Keytable for evga_indtube Remote Controller.
- 2015-04-16 11:06:12下载
- 积分：1
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Verilog数字系统设计教程(第二版) 夏宇闻
Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)
- 2020-06-20 18:40:02下载
- 积分：1
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squareLoop
利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)
- 2021-01-11 17:18:49下载
- 积分：1
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55593402DDS_vhdl
DDS分频实现，全部代码的完整过程，包括截图等(DDS divider to achieve the complete process of all the code)
- 2013-05-15 16:49:55下载
- 积分：1
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chengxu
设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键；
电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。
设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
- 2012-06-10 12:58:44下载
- 积分：1
