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Input_filter
Module for filtering input digital signal
- 2015-03-05 16:53:07下载
- 积分:1
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DE2_70_LTM_CCD
A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.
- 2009-10-04 23:27:04下载
- 积分:1
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基于FPGA实现数控机床高速运动的DDA设计
本文利用FPGA 可以弥补硬件插补器的不足,是执行速度提高,且可与运动控制部分很好的集成,制成运动控制器,实现高速运动控制
- 2022-03-10 10:19:20下载
- 积分:1
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cntrlr
verilog code for bus controller
- 2014-03-19 15:17:24下载
- 积分:1
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PWM
通过正弦波和三角波的比较产生SPWM波形(Through the comparison of sine wave and triangle wave produces SPWM waveform)
- 2016-12-23 14:36:56下载
- 积分:1
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rfid_re
VHDL实现 DDS。大家共享吧,一起学习,一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)
- 2008-05-16 15:12:13下载
- 积分:1
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多功能波形发生器VHDL程序与仿真
URAT VHDL程序与仿真
ASK调制与解调VHDL程序及仿真
LCD控制VHDL程序与仿真...
多功能波形发生器VHDL程序与仿真
URAT VHDL程序与仿真
ASK调制与解调VHDL程序及仿真
LCD控制VHDL程序与仿真-Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LCD control and simulation of VHDL
- 2023-06-27 23:35:04下载
- 积分:1
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QAM发生仿真
在Qaurtus环境下用Verilog输入实现64QAM信号的发生,用MATLAB协助验证,观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)
- 2021-03-02 23:39:33下载
- 积分:1
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55593402DDS_vhdl
DDS分频实现,全部代码的完整过程,包括截图等(DDS divider to achieve the complete process of all the code)
- 2013-05-15 16:49:55下载
- 积分:1
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PC
说明: Verilog HDL语言编写的32位程序计数器(PC)完整工程及相应仿真,QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)
- 2012-09-06 09:07:47下载
- 积分:1