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ddr_for_controller_and_phy
说明： 这是本人曾经参与的一个DDR controller接口项目，主要是FPGA rtl实现，仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)
- 2020-12-21 20:59:08下载
- 积分：1
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基于FPGA的ELM仿真
Efficient_Digital_Implementation_of_Extreme_Learning_Machines_for_Classification
- 2022-07-18 22:42:33下载
- 积分：1
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异步FIFO的设计 包括testbench 已调试成功
异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
- 2023-04-13 19:40:03下载
- 积分：1
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这是一本关于verilog编程语言的教程,对学习verilog语言有帮助
这是一本关于verilog编程语言的教程,对学习verilog语言有帮助-This is the one on the Verilog programming language tutorial, Verilog language learning has helped
- 2022-02-16 02:38:04下载
- 积分：1
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JOP字节码获取的源码，很重要，具体FPGA中实现
JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA
- 2022-01-26 02:39:47下载
- 积分：1
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脉冲宽度调制，编码，包括QuartusII和ModelSim工程…
脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
- 2023-05-09 12:15:03下载
- 积分：1
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Input_filter
Module for filtering input digital signal
- 2015-03-05 16:53:07下载
- 积分：1
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VHDL
VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC..(VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..)
- 2010-11-22 05:15:29下载
- 积分：1
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IIR-FPGA
基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)
- 2017-05-24 11:08:15下载
- 积分：1
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application-in-card-and-servo-drive
AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)
- 2012-03-22 12:44:52下载
- 积分：1
