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this is a verilog code about serial transmit receive.
this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
- 2022-11-29 07:45:03下载
- 积分：1
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moore-FSM
该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)
- 2013-05-10 10:27:09下载
- 积分：1
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mypro_synfifo
基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)
- 2020-09-22 01:27:56下载
- 积分：1
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CAM
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.
- 2014-12-06 00:33:45下载
- 积分：1
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QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus...
QuartusII简介手册+中文版
本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中
Quartus II 软件的功能。 不过，本手册并不是 Quartus II 软件的详尽参考手
册。 相反，本手册只是一本指导书，它解释软件的功能以及显示这些功能如
何帮助您进行 FPGA 和 CPLD 设计。-QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus II software for beginners, it provides an overview of programmable logic design in Quartus II software. However, this manual is not the Quartus II software, a detailed reference manual. Instead, this manual is a guide book, which explained the functions of the software and show how these features help you to FPGA and CPLD design.
- 2022-07-12 19:32:51下载
- 积分：1
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AHDL
AHDL语言介绍，很详细的介绍AHDL语言介绍，很详细的介绍(AHDL language introduction, a detailed explanation)
- 2009-11-17 15:27:59下载
- 积分：1
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GW48
vhdl语言试验箱GW48的各种模式引脚图。。(vhdl language the various modes of chamber GW48 pin map. .)
- 2010-01-20 13:20:28下载
- 积分：1
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DDR2_hardcore_userguide
xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)
- 2009-11-23 10:18:28下载
- 积分：1
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DES
说明： 自己写的DES的verilog实现。输入输出实现了并转串。(DES algorithm implemented in verilog.)
- 2020-12-03 16:19:25下载
- 积分：1
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PID
用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)
- 2012-03-09 11:18:17下载
- 积分：1
