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VHDL version of the C8051 core (C8051). Evatronix company s IP core
VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
- 2022-09-22 12:10:03下载
- 积分：1
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ecc
This paper analyzes the cryptography scheme of the Trust Platform Model(TPM). The focus of the discussion would be the comparison of elliptic curve cryptography and the nowadays widely used 2048-bit RSA in evaluating which would be better suited to be used on TPM. A TPM implementation scheme based on ECC is proposed, which includes encryption and decryption schemes, signature and verification scheme, key agreement scheme. Corresponding examples of TPM commands would also be given.
- 2019-06-13 14:53:45下载
- 积分：1
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基于VHDL的rsc（7,5）递归卷积编码器
rsc递归卷积编码器是turbo码的分量编码器，递归相对于普通的卷积码多了一个反馈，拥有更好地重量谱分布和更加的误码率特性，且码率越高，信噪比越低其优势越明显。利用D触发器组成的rsc生成器，逻辑思维简单，里面包含有测试波形以及测试的结果
- 2022-06-28 16:38:10下载
- 积分：1
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Kluwer.Academic.The.Verilog.Hardware.Description
Kluwer academic the verilog hardware description language fith edition
- 2014-10-08 08:11:42下载
- 积分：1
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8BIT_CPU
一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS
)
- 2020-07-01 09:00:02下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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Verilog代码。注册成功，对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-04-14 16:29:39下载
- 积分：1
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digital_clock
数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分：1
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fpga
说明： 中科院FPGA的课件！纯英文，比较简单，适合刚刚接触FPGA的小白！(Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!)
- 2020-03-19 14:19:16下载
- 积分：1
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add1A
用于实现锁相光子计数技术的累加器，verilog语言(Accumulator achieve specific cases for accumulator lock detection of photon counting technique)
- 2016-04-09 11:13:25下载
- 积分：1
