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Ffpga-jpegP
基于FPGA的JPEG图像压压缩，实现JPEG图像的实时压缩
(Real-time compression pressure compressed FPGA-based JPEG images, JPEG images)
- 2012-08-23 22:11:39下载
- 积分：1
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baugh wooley codes
这是用于阵列乘法器baugh wooley 。这是写Verilog代码。它表明8位阵列乘法。这是输入含有8,8每输出有15位
- 2023-06-03 10:00:03下载
- 积分：1
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Verilog LED 斯巴达 6
此代码是 verilog 代码和斯巴达 6 模型规范代码。欢迎大家下载、试用。谢谢大家的支持。
- 2022-03-01 23:14:35下载
- 积分：1
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multifreqvhdl
说明： 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)
- 2010-04-26 16:05:18下载
- 积分：1
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Altera-FPGA-sigmoid
利用quartus II 软件采用verilog语言设计了一个sigmoid激活函数(this work is a sigmoid ,use verilog language)
- 2018-11-22 15:31:29下载
- 积分：1
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modelsim_gaosi
说明： 用matlab将图片转成灰度图TXT，再通过verilog将数据导入FPGA中，采用高斯滤波算法来处理，再将处理后的图片数据导出到TXT中。(The image is transformed into gray-scale image TXT by MATLAB, and then the data is imported into FPGA by Verilog, processed by Gauss filter algorithm, and then the processed image data is exported to TXT.)
- 2020-05-28 16:20:09下载
- 积分：1
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DE2_115_TV
DE2-115开发板TV摄像头成像程序，源码亲测可用，可加入边缘算法成像，实时显示轮廓，速度流畅(The DE2-115 development board TV camera imaging procedures, the pro-test in the source can be added to the edge algorithms imaging, real-time display contours, fast-paced)
- 2020-07-09 19:18:55下载
- 积分：1
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Sdram_Control_4Port
使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)
- 2012-05-14 15:36:09下载
- 积分：1
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基于FPGA的信号发生器20140506
说明： 基于FPGA的芯片信号发生器，利用Verilog语言实现信号发生器的各个模块单元，
实现的要求：正弦波、三角波、方波等；(Based on FPGA chip signal generator, using Verilog language to realize each module unit of the signal generator, Requirements: sine wave, triangle wave, square wave, etc;)
- 2019-12-30 11:48:26下载
- 积分：1
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practica1
binary comparator with register
- 2012-04-24 17:39:04下载
- 积分：1
