登录
首页 » VHDL » 该程序实现的是n位全加器,首先用与非门实现一位全家器,最后实现n位的全加器。...

该程序实现的是n位全加器,首先用与非门实现一位全家器,最后实现n位的全加器。...

于 2022-01-24 发布 文件大小:20.90 kB
0 144
下载积分: 2 下载次数: 1

代码说明:

该程序实现的是n位全加器,首先用与非门实现一位全家器,最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • ADI_HDMI
    从FPGA输出到HDMI Tx的verilog 模块。实现完整HDMI图像输出功能。(FPGA output to HDMI Tx module in verilog)
    2020-12-17 11:09:12下载
    积分:1
  • 1.初始状态为4个方向的红灯全亮,时间1秒。 2.东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间30秒。 3.东、西方向黄灯闪烁,南、北方...
    1.初始状态为4个方向的红灯全亮,时间1秒。 2.东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间30秒。 3.东、西方向黄灯闪烁,南、北方向红灯亮。时间2秒。 4.东、西方向红灯亮,南、北方向绿灯亮。南、北方向通车,时间15秒。 5.东、西方向红灯亮,南、北方向黄灯闪烁。时间2秒。 6.返回2,继续运行。 -1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.
    2023-01-12 03:20:04下载
    积分:1
  • FPGA
    基于FPGA的VHDL编程实现各种音频信号,采用的是周立功公司的fusion_startkit开发板。-FPGA-based VHDL Programming realize a variety of audio signals, are used by companies fusion_startkit weeks Ligong development board.
    2022-07-15 20:29:13下载
    积分:1
  • polyPhaseFilter
    说明:  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)
    2019-12-24 09:58:51下载
    积分:1
  • Copy
    this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device
    2020-06-21 21:00:02下载
    积分:1
  • 这个RAR文件包含有关FPGA和CPLD的呈现。
    This rar files contains the presentation about FPGA and CPLD .
    2022-07-13 06:31:38下载
    积分:1
  • 这里面有许多vhdl的例子,相信对这语言的初学者受益匪浅
    这里面有许多vhdl的例子,相信对这语言的初学者受益匪浅-There are many examples of vhdl, I believe that beginners benefit from this language
    2023-06-28 10:40:04下载
    积分:1
  • fir
    vhdl code for fir filter
    2011-02-18 11:51:26下载
    积分:1
  • 16 floating
    16卫浮点FFT算法的VHDL实现,有测试文件。-16 floating-point FFT algorithm Wei VHDL realize, have the test paper.
    2023-03-07 14:45:03下载
    积分:1
  • verilog实现自动售货机
    说明:  能实现输入0.5 1 5块钱的累加,然后对应购买的商品价格进行比较,显示找的钱数或错误灯(MY English is very good)
    2019-01-09 13:35:02下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载