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512×8bid的FIFO 含工程文件，基于QUARTUs
512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
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- 积分：1
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polyphaseFIR_1v0
polyphase fir dilter
- 2016-02-19 21:32:07下载
- 积分：1
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VHDL version of the C8051 core (C8051). Evatronix company s IP core
VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
- 2022-09-22 12:10:03下载
- 积分：1
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ADc
与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)
- 2021-03-29 11:19:10下载
- 积分：1
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VHDL语言描述的二进制十进制译码电路，已经编译完成
VHDL语言描述的二进制十进制译码电路，已经编译完成-Binary decimal decoder circuit
- 2022-02-22 00:13:01下载
- 积分：1
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XilinxISE9.2andChinpScopePro9.2Sn
Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
- 2021-03-29 15:29:11下载
- 积分：1
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fft_8
基二8点fftverilog实现。经过modelsim仿真通过(Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation)
- 2021-02-21 16:49:42下载
- 积分：1
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OFDM-system-FPGA-design
说明： OFDM基带处理的书籍和论文，以及发送和接收端源码。(OFDM baseband processing books and papers, as well as send and receive source code.)
- 2020-06-06 13:54:22下载
- 积分：1
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在vhdl开发环境下，关于协议PS2 verilog 源码
在vhdl开发环境下，关于协议PS2 verilog 源码-In VHDL development environment, with regard to the agreement PS2 verilog source code
- 2022-05-06 00:46:27下载
- 积分：1
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lic_Xilinx_ISE_Vivado
这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)
- 2013-04-26 14:51:09下载
- 积分：1
