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i2c_reader
一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)
- 2013-07-31 09:25:56下载
- 积分：1
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键盘接口电路的一个工程
键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件-Keyboard interface circuit of a project--- including VHDL source code and compile the relevant documents after
- 2022-05-19 23:52:35下载
- 积分：1
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NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
基于NIOS II的SD CARD MUSIC PLAYER源码，包括硬件SOPC-NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
- 2023-02-13 09:35:05下载
- 积分：1
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Written in the quaters of the size of the comparator output, verilog language wr...
在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory
- 2022-02-26 07:00:13下载
- 积分：1
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VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELLO的程序
VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)
- 2020-07-08 20:28:56下载
- 积分：1
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mutiplier
说明： 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证(Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification)
- 2009-08-28 13:28:04下载
- 积分：1
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navigation
Ship navigation project
- 2014-12-04 18:58:16下载
- 积分：1
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MAX+plus II编译的模30加法计数器，简单的与非门组成！
MAX+plus II编译的模30加法计数器，简单的与非门组成！-MAX+ Plus II compiler module adder 30 counters, a simple composition with the non-door!
- 2022-04-18 02:27:03下载
- 积分：1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分：1
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8 位修改 Booth 型乘法器
这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......
- 2022-01-24 13:25:05下载
- 积分：1
