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State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）
State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
- 2023-06-02 11:25:02下载
- 积分：1
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合众大公司XILINX_V4实验箱原理图
合众大公司XILINX_V4实验箱原理图-United XILINX_V4 large companies schematic experimental box
- 2022-12-12 08:15:03下载
- 积分：1
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CFO
这是基于MIMO-OFDM的对CFO进行估计的源程序，对分析此同步算法有着非常重要的作用。(This is based on the source of the MIMO-OFDM of the CFO estimation, on the analysis of this synchronization algorithm has a very important role.)
- 2012-12-13 15:29:51下载
- 积分：1
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MRAM2012
STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确(STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct)
- 2020-06-29 14:20:02下载
- 积分：1
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xlj
说明： ilx554b型号CCD积分时间程序的设计，包括两座控制信号(program for ilx554b,the driver include two parts single)
- 2010-04-13 00:57:00下载
- 积分：1
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This code that genetes a square, sawtooth and a triangular waveform. It is usefu...
This code that genetes a square, sawtooth and a triangular waveform. It is useful for designing a function generator in VHDL.
- 2022-07-04 20:04:24下载
- 积分：1
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ieee
VLSI Implementation IEEE Papers 2010 to 2014
- 2014-07-08 03:52:41下载
- 积分：1
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Ａ８２５５的ｖｈｄｌ源代码，比较简单的一个
Ａ８２５５的ｖｈｄｌ源代码，比较简单的一个-Vhdl source code of A8255
- 2022-05-07 14:31:39下载
- 积分：1
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widgets
CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)
- 2014-10-31 09:25:37下载
- 积分：1
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cpld/fpga common adder Verilog design procedures
cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
- 2022-08-19 10:20:20下载
- 积分：1
