-
VHDL开发环境,四人抢答器,实现了四个人能同时抢答的功能。...
VHDL开发环境,四人抢答器,实现了四个人能同时抢答的功能。-VHDL development environment Answer four, and the realization of the four functions at the same time Answer.
- 2022-07-26 14:54:56下载
- 积分:1
-
DW8051_ALL
包中包括,
DW8051完整的Verilog HDL代码
两本手册:
DesignWare Library DW8051 MacroCell, Datasheet
DesignWare DW8051 MacroCell Databook
三篇51论文:
基于IP 核的PSTN 短消息终端SoC 软硬件协同设计
Embedded TCP/ IP Chip Based on DW8051 Core
以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)
- 2021-05-07 09:28:36下载
- 积分:1
-
EP1C6_EP1C12核心板原理图,方便自己动手做板学习FPGA
EP1C6_EP1C12核心板原理图,方便自己动手做板学习FPGA-EP1C6_EP1C12 core board schematics, do-it-yourself to do to facilitate learning FPGA board
- 2022-07-11 04:51:07下载
- 积分:1
-
ADC_TCL5510-verilog
verilog 驱动TLC5510代码,TLC5510是高速的AD,可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)
- 2020-08-13 21:28:29下载
- 积分:1
-
DDR3_user_design
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器,里面生成了Core,可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)
- 2012-02-02 15:16:00下载
- 积分:1
-
简易cpu的设计
计算机组成原理的课程设计作业,用vhdl语言写了一个简易的cpu,包括寄存器,存储器等原件,完全用代码写成,没有直接用原件去连接,有助于我们很好的学习vhdl。 这是一个cpu的连接代码,并没有各种原件的代码 ,因为各个原件代码很简单就没上传
- 2022-03-12 07:35:18下载
- 积分:1
-
能够实现8位的无符号数的乘除法,模拟了笔算的过程
- 2022-12-11 10:00:03下载
- 积分:1
-
Realize with a clock input, can realize multi
实现同一个时钟输入,可以实现多分频,在一个时钟的驱动下-Realize with a clock input, can realize multi-frequency, in a clock-driven
- 2023-02-21 01:50:03下载
- 积分:1
-
huawei
华为内部资料,包括verilog电路设计,硬件工程师手册,verilog约束,synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)
- 2015-07-11 20:08:52下载
- 积分:1
-
并串转换模块,内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。...
并串转换模块,内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
- 2022-01-25 21:05:32下载
- 积分:1