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利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块...
利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module
- 2022-02-25 00:52:03下载
- 积分：1
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generate-white-noise-with-fpga
一共7篇文章，介绍了使用fpga产生任意分布白噪声的方法，值得借鉴(A total of seven articles, describes using fpga to generate arbitrary distribution of white noise, it is worth learning)
- 2012-12-21 16:41:35下载
- 积分：1
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watch
数字钟，简单的数电应用，电子表源程序，常用也使用-watch
- 2022-04-18 14:17:50下载
- 积分：1
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sqr
VHDL CODE FOR SQUARE WAVE GENERATOR
- 2014-01-22 17:14:20下载
- 积分：1
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FPGA测试程序SignalTap
AD9235FPGA编程 可AD采集信号 信号频谱检测 检测任意波形输入(AD9235FPGA programming allows AD to collect signal and spectrum detection and detect arbitrary waveform input.)
- 2020-11-24 20:39:34下载
- 积分：1
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ieee1588_megacore_fpga_ip
IEEE1588de FPGA 程序，已测试，可直接用，方便(IEEE1588de FPGA program has been tested, can be directly used to facilitate)
- 2021-03-26 11:59:13下载
- 积分：1
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cpu
用全加器设计8位运算器逻辑电路图
2、根据逻辑电路用 VHDL编程实现
3、调试编译通过后，仿真
(this file can help you learn the design of cpu)
- 2010-01-05 09:56:11下载
- 积分：1
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016_versat_updown_counter
说明： Verilog实现的加减法功能计数器，通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
- 2019-11-27 23:16:27下载
- 积分：1
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ps2
使用verliog实现ps2键盘接口的驱动，通过altera cyclone 第四代验证通过(Use verliog implement ps2 keyboard interface driven by a fourth-generation verified by altera cyclone)
- 2015-12-17 16:28:38下载
- 积分：1
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qpsk
说明： 载波同步是QPSK信号相干解调的一项关键技术。(Carrier synchronization signal coherent QPSK demodulation is a key technology.)
- 2008-10-07 10:12:23下载
- 积分：1
