登录
首页 » VHDL » watch

watch

于 2022-04-18 发布 文件大小:6.26 kB
0 108
下载积分: 2 下载次数: 1

代码说明:

数字钟,简单的数电应用,电子表源程序,常用也使用-watch

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • vga_interface_requiring_core_regeneration
    vga interface with text rom. font size 80x40. core need core regeneration.
    2013-05-19 02:09:10下载
    积分:1
  • mux8to1_with_if
    this code to input 8 different data and make them out sequentialy
    2015-02-19 10:54:20下载
    积分:1
  • blocking
    基于verilog语言的数据选择器,包括数据选择器的测试模块 (verilog language based on the data selector, including data selection for the test module)
    2007-03-22 09:05:10下载
    积分:1
  • chuankou_huihuan
    FPGA与PC端实现串口数据的收发,先从PC端接收数据,然后发回给电脑,可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)
    2020-06-16 10:20:01下载
    积分:1
  • veye_mipi
    说明:  1、 例程功能VEYE-290-LVDS模组视频接入演示。(显示设备必须支持1080p/30或1080p/25的帧率) Veye模组—>MIA701开发板—>HDMI显示设备 2、 本例程硬件平台 MIA701-PCIE开发板,FPGA芯片:XC7A100TFGG484 3、 软件平台Vivado2018.1。 4、 附件含开发板原理图(底板+核心板)(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))
    2019-04-01 11:08:04下载
    积分:1
  • 8.25
    改写四号中断的 自己编的,,,,,,求过啊!!!一个很简单的小程序(Rewrite the fourth interruption of their series,,,,,, begged ah! ! ! A very simple little program)
    2013-12-16 20:46:33下载
    积分:1
  • stap_steering
    这个verilong代码实现的功能是radar processing的功能。(This verilong code function is radar processing functions.)
    2015-07-21 00:59:39下载
    积分:1
  • FPGA源代码
    FPGA源代码公布,包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序,LED静态显示ADC0809 VHDL控制程序,DAC0832 接口电路程序
    2022-04-26 16:23:11下载
    积分:1
  • USB2.0的IP核(详细verilog源码和文档)
    USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
    2020-12-24 18:49:04下载
    积分:1
  • yidong_top_xu
    本实验实现了一个小的乒乓游戏,VGA显示,代码下载的FPGA板子上验证通过,效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)
    2011-11-01 19:37:44下载
    积分:1
  • 696518资源总数
  • 105885会员总数
  • 31今日下载