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all clock
说明： 数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:01下载
- 积分：1
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z_max_spwm
Z源逆变器简单升压模拟仿真。调制方式为SPWM，通过设置三角波幅值和比较电压，即可调节输出电压。(Z-source inverter simple step-up simulation. Modulation mode SPWM, by setting the the triangle amplitude and the comparison voltage to regulate the output voltage.)
- 2020-11-02 19:09:53下载
- 积分：1
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vhdl_quick-learn
vhdl learnig material............
- 2015-08-07 19:09:24下载
- 积分：1
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uart_byte_rx
说明： libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分：1
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Huffman
用VHDL编写的huffman编码的源程序(With the VHDL source code written in huffman coding)
- 2010-06-08 14:58:32下载
- 积分：1
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Verilog_Ip_RAM
说明： altera ram ip教程。对RAM进行读写操作，写32个数据到RAM中，再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)
- 2020-08-17 11:38:21下载
- 积分：1
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digital-PLL
收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。(Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.)
- 2015-02-11 10:39:31下载
- 积分：1
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11-07-11
AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)
- 2013-09-16 10:52:00下载
- 积分：1
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digital-processing-with-FPGA
vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)
- 2016-07-22 21:53:49下载
- 积分：1
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goodProcessor.srcs
说明： 处理器系统，处理器加上存储器，从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)
- 2020-10-10 23:10:02下载
- 积分：1
