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基于FPGA的DDR3控制器
这个代码为基于XILINX FPGA的DDR3控制部分，实用性很强，忍痛拿来分享，望各位笑纳。
- 2022-04-13 09:35:34下载
- 积分：1
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16bit-Mulitiplier-Verilog-procedure
这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)
- 2012-12-25 11:33:48下载
- 积分：1
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code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分：1
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prtsc
Program for simulate a prtsc
- 2015-09-29 21:54:37下载
- 积分：1
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progconterful
four bit counter verlog source code for veriwell including test bench
- 2010-03-29 18:54:45下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
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cmv2000
CMV2000采集的数据，进行图像的位对齐，图像的预处理
- 2022-01-31 10:30:47下载
- 积分：1
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赛灵思ddr3控制器
赛灵思ddr3控制器xilinx_ddr3_mig_x32_400mhz，在镁光DDR3上验证通过，位宽32bit，频率800M，改进了时钟生产模块，能够适应任何频率外部时钟。赛灵思ddr3控制器xilinx_ddr3_mig_x32_400mhz，在镁光DDR3上验证通过，位宽32bit，频率800M，改进了时钟生产模块，能够适应任何频率外部时钟。
- 2022-12-27 19:55:08下载
- 积分：1
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用FPGA verilog hdl模拟类I2C通信
用FPGA verilog hdl模拟类I2C通信
- 2022-02-25 01:16:56下载
- 积分：1
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masera2017
fpga hardware hevc implementation
- 2018-08-06 01:26:57下载
- 积分：1
