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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分：1
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fifo16_16
异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
- 2020-10-26 10:49:59下载
- 积分：1
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vending-machine
用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分：1
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Xilinx_2018_Licenses_Downloadly.ir
说明： Xilinx Licenses 2018
- 2020-06-25 08:20:01下载
- 积分：1
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source
完成cmos摄像头对图像的捕捉，然后进行拼接通过USB进行传输。(complete picture capture)
- 2020-11-11 18:19:45下载
- 积分：1
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REMOTE
orcad schematics for 8051 with rtc and lcd
- 2011-12-01 07:11:52下载
- 积分：1
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1
说明： led blinking program.................
- 2012-01-12 18:05:09下载
- 积分：1
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tb_modular
Matlab to hdl code for Least_square testbench
- 2020-06-17 12:20:02下载
- 积分：1
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multiplier
参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )
- 2011-12-08 15:14:04下载
- 积分：1
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VHDL
A Full adder using half adder unit in vhdl
- 2010-01-05 11:39:14下载
- 积分：1
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