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Interface design between microprocessor and cpld ,suit for IC design and applica...
cpld与单片机接口设计,利于电子设计及应用- Interface design between microprocessor and cpld ,suit for IC design and application
- 2022-03-25 22:52:32下载
- 积分：1
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设计含异步清零和同步时钟使能的加法计数器
设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter
- 2023-03-27 21:05:03下载
- 积分：1
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mux21a
在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)
- 2008-12-24 18:25:20下载
- 积分：1
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Synchronous Resets Asynchronous Resets I am so confused! How will I ever know wh...
Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper
- 2022-03-02 03:52:16下载
- 积分：1
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课程设计-数字钟
说明： 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)
- 2020-05-18 17:11:07下载
- 积分：1
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bpsk-qpsk
this is bpsk code in matlab
- 2011-10-20 02:49:32下载
- 积分：1
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WM8731_WM8731L
wm8731音频编解码芯片使用介绍,该手册里面对该芯片进行了详细的描述，对各个单元模块也进行了详细的阐述(the handbook of WM8721/WM8731L)
- 2010-05-20 10:47:30下载
- 积分：1
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Verilog 下 16位除法算法程序，高精度，固定17个时钟周期
Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
- 2022-01-27 13:18:06下载
- 积分：1
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交通管理与控制系统
交通灯管理与控制系统-客户端与云网络连接并从远程位置控制的交通灯系统推导
- 2022-11-15 23:50:03下载
- 积分：1
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ofdm_quartus_v72
说明： OFDM的简易verilog仿真程序，环境是quartus，版本需要7.2以上(OFDM Modulation and Demodulation using Verilog in Quartus)
- 2009-08-30 21:58:25下载
- 积分：1
