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dds算法的fpga实现 altera
根据不同设置，输出不同频率的信号源...
dds算法的fpga实现 altera
根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
- 2022-03-02 02:14:19下载
- 积分：1
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FPGA设计软件的绝佳入门书籍，本人珍藏，全部吐血奉献之2，请大家赶紧下！...
FPGA设计软件的绝佳入门书籍，本人珍藏，全部吐血奉献之2，请大家赶紧下！-FPGA design software, an excellent entry-books, I treasure all the blood sacrifice of 2, please hurry under the U.S.!
- 2022-07-17 20:40:02下载
- 积分：1
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Electronic and system matlab simulation
Electronic and system matlab simulation
- 2023-07-05 12:50:04下载
- 积分：1
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mdct_latest.tar
mdct, it contains DOC,MATLAB,source,synthesis.
- 2009-12-11 14:15:39下载
- 积分：1
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verilogppt
北航夏宇闻的Verilog的PPT讲稿，挺经典的，适合初学者学习(Northern Xia Yu Wen' s Verilog the PPT script, very classic, suitable for beginners to learn)
- 2011-06-16 11:32:45下载
- 积分：1
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sd_models_verilog
测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)
- 2021-02-26 20:09:37下载
- 积分：1
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Three-Pulse-VSR-
对三相电压型逆变器的数学模型进行了详细的数学推导，简单容易理解(Three-phase voltage inverter for the mathematical model of a detailed mathematical derivation is simple and easy to understand)
- 2011-08-14 22:30:28下载
- 积分：1
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verilog_median_filter
图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)
- 2016-01-24 16:54:32下载
- 积分：1
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MIPS_LANG
verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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这是一个数字时钟数字逻辑电路，整个工程包上传…
这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
- 2022-08-06 10:22:24下载
- 积分：1
