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rc-evga-indtube
evga-indtube.h - Keytable for evga_indtube Remote Controller.
- 2015-04-16 11:06:12下载
- 积分：1
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blessing3.9.6
Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。
使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。
合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。
(Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1.
Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually.
Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)
- 2015-04-15 22:45:03下载
- 积分：1
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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
)
- 2013-09-05 20:04:36下载
- 积分：1
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miaob
电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)
- 2010-05-10 11:25:55下载
- 积分：1
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dr6—ise-F
用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
- 2017-10-11 21:19:55下载
- 积分：1
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RS_255_223_ENCODER
rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)
- 2015-03-30 09:52:09下载
- 积分：1
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zhentongbu_VerilogHDL
帧同步的VHDL程序源代码，巴克码同步实现。(Frame synchronization of the VHDL source code, Barker code synchronization)
- 2012-05-26 19:35:40下载
- 积分：1
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16_QAM
用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)
- 2013-09-02 16:23:40下载
- 积分：1
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fenpin
这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)
- 2013-11-17 15:01:30下载
- 积分：1
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matlab
真是基于matlab的QPSK，格雷码，瑞利衰减信道，加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)
- 2021-03-16 22:39:21下载
- 积分：1
