登录
首页 » VHDL » 频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分...

频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分...

于 2022-01-25 发布 文件大小:88.05 kB
0 128
下载积分: 2 下载次数: 1

代码说明:

频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz); 当输入信号的频率大于相应量程时,有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measurement range of 1MHz, the measured value through the four LED 8421BCD code shows the form of output can be controlled through the switch range, range at 10kHz, 100kHz, 1MHz Three (maximum reading were 9.999kHz, 99.99kHz, 999.9kHz) when the input signal is greater than the corresponding frequency range, it shows overflow.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • LED 闪烁的VHDL代码
    LED闪烁的VHDL代码
    2022-07-28 10:23:55下载
    积分:1
  • arm
    ARM教程,理解精辟,言简意赅,不错哦,欢迎大家看看(arm language )
    2009-02-18 20:06:42下载
    积分:1
  • CameraLink_Oserdes2_test
    40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )
    2014-02-25 14:06:38下载
    积分:1
  • cycloneII Quartus verilog to develop a simple sequential circuit
    cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit
    2022-03-01 09:19:56下载
    积分:1
  • fifo16_16
    异步的fifo,写时钟和读时钟相互独立,能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
    2020-10-26 10:49:59下载
    积分:1
  • VHDL ip core的设计,软核的设计方法
    VHDL ip core的设计,软核的设计方法-VHDL core of the design, soft-core design
    2022-06-01 06:05:02下载
    积分:1
  • final-delivery
    Block LU decompostion of a matrix
    2014-10-08 15:33:16下载
    积分:1
  • sdram-source
    SDR SDRAM 控制器的源代码 altera公司的(source code from altera)
    2010-06-09 19:35:03下载
    积分:1
  • Quartus II TimeQuest时序分析器说明书
    说明:  Quartus II TimeQuest 时序分析器说明书;这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识,以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)
    2020-08-07 17:48:31下载
    积分:1
  • 整个工程代码
    掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序,熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
    2019-01-21 17:21:27下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载