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fft_ex1
基于verilog的FFT设计，使用vivado作为开发平台(Verilog based on the FFT design, the use of vivado as a development platform)
- 2021-02-24 23:39:39下载
- 积分：1
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FPGA_UART
用Verilog语言实现的FPGA UART独立收发模块
思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond.
功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)
- 2011-10-03 13:18:56下载
- 积分：1
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基于FPGA的等精度计频器
资源描述
本设计中可以实现测量周期，测量方波的占空比，被测范围1Hz-100MHz。相对误差小于0.001%.
可以测方波、正弦波等波型。同时还有上下左右按键控制显示
- 2022-03-29 07:43:32下载
- 积分：1
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13.2_MotionDetec
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)
- 2020-10-23 20:57:22下载
- 积分：1
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clkdiv
基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)
- 2018-06-10 17:08:57下载
- 积分：1
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fir_vivado
此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of
the generation of the signal of sin and the
design of fir filter and the ari)
- 2016-09-18 15:00:22下载
- 积分：1
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sram
说明： FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)
- 2019-08-19 16:03:39下载
- 积分：1
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adaptive
这是基于MATLAB编程实现自适应滤波器，并在XILINX的FPGA上硬件可实现的模型文件(This is based on the MATLAB programming adaptive filter, and the XILINX' s FPGA hardware can be a model document)
- 2009-06-24 13:26:32下载
- 积分：1
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Manip_NIOS_1
nios processor example 1
- 2015-05-22 00:17:43下载
- 积分：1
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CRC
10G网络 CRC-32 CRC-64计算代码(10G Network CRC-32 CRC-64 Computing Code)
- 2020-06-22 19:20:01下载
- 积分：1
