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ditietickets
利用VHDL语言实现地铁售票系统的设计。售票系统根据途经站数自动计算票价(Using VHDL language metro ticket system. Ticketing system automatically calculated according to the number of fares via station)
- 2010-05-07 17:09:35下载
- 积分：1
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256M_sdram_OK
改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分：1
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ZHWX
DDS
产生正弦信号，OOK，AM三种波形。
使用xilinx FPGA VHDL(DDS.
Resulting in sinusoidal signal, OOK, AM three waveforms.
Using xilinx FPGA VHDL.)
- 2016-09-23 16:01:04下载
- 积分：1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分：1
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中值滤波
在图像中
- 2023-06-24 17:20:03下载
- 积分：1
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juanjima
231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创！！！！(Verilog achieve 231 convolutional code, preceded by a detailed description of the document, the source, the absolute originality! ! ! !)
- 2013-01-18 10:35:31下载
- 积分：1
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GPS
通过UART在FPGA数码管上显示经纬度坐标的代码(By UART displayed on FPGA digital latitude and longitude coordinates of the code)
- 2015-06-22 17:14:37下载
- 积分：1
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FPGA正弦信号发生器
基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)
- 2020-11-10 10:59:46下载
- 积分：1
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modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！...
modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!
- 2022-04-23 10:16:49下载
- 积分：1
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HDB3_encoder_QuartusPrj
说明： HDB3编码Quartus2 10.0的工程，modelsim仿真，有实物图、仿真图以及源程序，适合做通信原理课程设计的同学参考使用(HDB3 encoding Quartus2 10.0 project, modelsim simulation, there are physical map, simulation diagrams and source code, suitable for students of communication theory courses designed for reference use)
- 2011-03-25 08:35:32下载
- 积分：1
