登录
首页 » VHDL » VHDL实现SPI功能源代码

VHDL实现SPI功能源代码

于 2022-01-26 发布 文件大小:63.86 kB
0 102
下载积分: 2 下载次数: 1

代码说明:

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • HDB3-encoderauncoder
    HDB3编码器与解码器,以及RTL图,使用Verilog HDL实现(HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement)
    2014-12-14 13:17:26下载
    积分:1
  • FSK信号发生器,基于VHDL语言,好用的!
    FSK信号发生器,基于VHDL语言,好用的!-FSK signal generator, based on the VHDL language, useful!
    2022-06-19 14:00:10下载
    积分:1
  • complex_timing_by_Primetime
    用PrimeTime的技巧,解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
    2012-08-05 19:07:47下载
    积分:1
  • 这里面有许多vhdl的例子,相信对这语言的初学者受益匪浅
    这里面有许多vhdl的例子,相信对这语言的初学者受益匪浅-There are many examples of vhdl, I believe that beginners benefit from this language
    2023-06-28 10:40:04下载
    积分:1
  • Block-cipher-lock
    密码锁verilog源代码,包括四个七段数码管显示模块,设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
    2014-01-11 23:57:19下载
    积分:1
  • fpga_pc_software
    计算机组成原理课程实验使用软件,Thinpad教学机教学实验软件 实现mips代码到机器代码之间的转换 实现本机和FPGA板的通信,将机器代码送入 可在本机编写代码送入fpga板的sram中,fpga板的cpu会运行(Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine code conversion for communication between the machine and the FPGA board can be fed into the machine code written in native code into the fpga board sram in, fpga board cpu runs)
    2014-06-15 18:10:11下载
    积分:1
  • SDRAM
    基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
    2018-01-16 11:24:03下载
    积分:1
  • fir.tar
    FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)
    2004-10-19 10:14:56下载
    积分:1
  • 这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着...
    这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
    2022-05-13 15:53:30下载
    积分:1
  • fpga under the seven
    fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University
    2022-02-13 12:54:58下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载