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8253
8253可编程定时器/计数器芯片 VeriLog实现(8253 programmable timer/counter chip VeriLog achieve)
- 2013-05-31 20:40:23下载
- 积分：1
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AM-modulated-learning-ladder
AM modulated learning ladder
- 2015-07-15 09:42:45下载
- 积分：1
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使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为...
使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为-10DB-CDMA system using MATLAB to complete the relevant receivers, which Hadamard matrix of 128 bands, simulation-10DB-bit signal to noise ratio for
- 2022-06-27 04:04:51下载
- 积分：1
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MCU and FPGA communication functions: SCM control FPGA to write a byte of data...
单片机与ＦＰＧＡ的通信
功能 :单片机控制写FPGA一字节数据
单片机控制写FPGA一字节数据时钟 (注意读写数据端口可复用,也可分用)
单片机控制发送数据端口
-MCU and FPGA communication functions: SCM control FPGA to write a byte of data SCM control FPGA to write a byte of data clock (Note that the read and write data ports can be re-used, but also can be divided into use) SCM control to send data port
- 2023-04-21 07:05:03下载
- 积分：1
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DPLL
基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码
(DPLL)
- 2010-05-11 19:34:11下载
- 积分：1
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- 2023-04-14 01:30:04下载
- 积分：1
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it performs the serail dividing operations
it performs the serail dividing operations
- 2022-11-07 21:55:03下载
- 积分：1
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verilog-axi-master
说明： Verilog AXI Components Readme
GitHub repository: alexforencich verilog-axi
- 2020-11-04 14:39:51下载
- 积分：1
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这些是Verilog文件但我上传文本格式（记事本）
these are verilog files but i am uploading in text(notepad) format
- 2022-12-19 09:00:04下载
- 积分：1
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esvl
MATLAB Filter Design HDL Coder
Simunlink HDL Coder
Xilinx ISE Webpack
- 2011-06-15 19:56:11下载
- 积分：1
