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基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙,秒,分。
有开始,暂停,复位功能。
学习...
基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙,秒,分。
有开始,暂停,复位功能。
学习VerilogHDL的经典例子,添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
- 2022-12-27 19:50:04下载
- 积分:1
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TimeGen3
能够绘制数字电路的时序图,是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)
- 2017-12-27 19:34:23下载
- 积分:1
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spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!...
spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!-spartanII Xilinx is provided by a high-performance chip FGPA, spartanII This paper describes the architecture and programming!
- 2022-03-03 02:06:35下载
- 积分:1
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I2C is a two
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices.
- 2022-10-23 17:25:02下载
- 积分:1
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Temperature measurement
Using LabVIEW FPGA, Spartan3E, PMODTMP
Temperature measurement
Using LabVIEW FPGA, Spartan3E, PMODTMP
- 2022-03-05 00:22:10下载
- 积分:1
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4x4 KEYPAD median counter input, input their own definition of the median
4X4 KEYPAD 的输入位数计数器,可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median
- 2022-01-27 22:09:15下载
- 积分:1
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pin_lv1
一个简易的频率计,主要用检测在一定范围内的频率,当然频率过大会有误差(A simple frequency meter, mainly used for testing in a range of frequencies, of course, frequency of errors over the General Assembly)
- 2010-06-05 10:30:56下载
- 积分:1
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04_led_test
说明: FPGA控制外边led,并实现跑马灯等多种效果,用户可以自行控制(FPGA control outside led)
- 2020-06-16 09:40:02下载
- 积分:1
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shukongfenpinqi
数控分频器的设计
数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)
- 2008-12-13 09:56:51下载
- 积分:1
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bpsk-qpsk
this is bpsk code in matlab
- 2011-10-20 02:49:32下载
- 积分:1