-
saa7113_vhdl-config
saa7113_配置.SAA7113视频解码系列芯片的一种,8位彩色配置(saa7113_ configuration. SAA7113 video decoder chips in an 8-bit color configuration)
- 2013-11-26 08:57:58下载
- 积分:1
-
Optimised_OMP
一种压缩感知信号恢复算法,针对贪婪迭代类算法中的正交匹配追踪(OMP)算法的改进。OMP在每次迭代过程中选择出的原子并不是最优的,无法使本轮迭代中残差的减少最大化。本例程实现了改进的最优OMP算法,即Optimised_OMP,保证每次迭代选出的原子与已选出的原子序列所构成的平面正交,因而可以使残差下降的更快,从而加速算法收敛。(A compressed sensing signal recovery algorithms track (OMP) algorithm and orthogonal matching algorithm greedy iterative class. The OMP selected atoms in each iteration of the process is not optimal, not be able to maximize the reduction of the residual in the current round of iteration. The routines to achieve the optimal OMP algorithm improvements that Optimised_OMP, to ensure that each iteration selected atoms with atomic sequence elected a plane orthogonal, and thus can make the residuals have declined even faster, thus speeding up the algorithm convergence.)
- 2021-03-08 10:19:29下载
- 积分:1
-
LED7s
七段LED数码管显示译码器设计,将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)
- 2021-04-23 23:28:47下载
- 积分:1
-
CPLD / FPGA解码器RS(204188)of the Verilog程序
cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
- 2023-05-10 18:05:03下载
- 积分:1
-
verilog_lab_solution
Verilog 实验代码。。。经典的,里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)
- 2011-12-01 23:44:40下载
- 积分:1
-
5L_SVPWM_ANPC_CPLD
基于CPLD硬件描述语言编写的五电平SVPWM脉冲触发程序(Five level SVPWM pulse trigger program based on CPLD hardware description language)
- 2020-12-14 16:19:15下载
- 积分:1
-
The design of digital self
数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
- 2022-08-10 00:17:42下载
- 积分:1
-
counter-with-T_FF
This is counter with T_FF.
- 2016-03-26 16:36:05下载
- 积分:1
-
2ASK
2ask调制与解调的源代码,经过测试可用(2ask modulation and demodulation source code is available, tested)
- 2012-12-09 21:27:49下载
- 积分:1
-
VHDL_Snake_Game
在FPGA开发板上用VHDL语言实现了贪吃蛇游戏,开发软件为quartus 2.这是详细的实验报告,包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)
- 2012-06-25 16:15:26下载
- 积分:1