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使用Verilog HDL的全加器的设计
一个全加器和，增加了二进制数和帐户进行的值以及。一一位全加器加三一位数字，通常写成 ；A，B，和 ； ；CIN； ；一 ；和 ；B ；是操作数，和 ；CIN ；是一位从以前的少重要阶段。[ 2 ] ；全加器通常是在一个级联的加法器的一个组成部分，其中添加8、16、32，等位的二进制数。该电路产生一二位输出，输出端和通常由信号 ；cout ；和 ；S，
- 2022-12-29 08:15:03下载
- 积分：1
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4位二进制同步计数器
用Verilog语言实现4位二进制同步计数器的功能(Write a program in Verilog language to implement the fouction of Four binary synchronous counters.)
- 2020-11-20 15:19:37下载
- 积分：1
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基于Basys3的贪吃蛇小游戏
基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)
- 2021-03-10 20:39:26下载
- 积分：1
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GUI
1）选择一个语音信号作为分析对象，或录制一段语音信号； 2）对语音信号进行采样，画出采样前后语音信号的时域波形和频谱图； 3）利用MATLAB中的随机函数产生噪声加入到语音信号中，使语音信号被污染，然后进行频谱分析； 4）设计用于处理该语音信号的数字滤波器，给出滤波器的性能指标，画出滤波器的频率响应； 5）对被噪声污染的语音信号进行滤波，画出滤波前后信号的时域波形和频谱，并对滤波前后的信号进行比较和分析； 6）回放各步骤的语音信号，给出相应处理程序及运行结果分析。(1) Select a voice signal as an analysis object, or record a voice signal 2) sampling the voice signal, draw the waveform and frequency spectrum of the time domain before and after sampling the speech signal 3) using the random function in MATLAB generated noise was added to the speech signal, the speech signal to be contaminated, and then spectrum analysis 4) for processing the speech signal, the digital filter design, given the performance of the filter to draw the filter' s frequency response 5) on the noise pollution of the speech signal is filtered, time-domain waveform and spectrum draw before and after filtering the signal before and after filtering, and the signal for comparison and analysis 6) playback of the speech signal for each step, given the results of the corresponding processing procedures and run analysis.)
- 2021-03-18 17:29:19下载
- 积分：1
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FPGA的串口通信verilog代码
基于FPGA平台的verilog语言编写的uart串口通信代码，可以实现发射和接收，并附有multism仿真代码。可以实现功能。Uart serial communication code written based on FPGA platform verilog language can realize transmit and receive, with multism simulation code. Can achieve the function.
- 2022-09-15 02:40:03下载
- 积分：1
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VGA显示程序，显示生日快乐
程序是自己编写的，程序的主要功能是实现VGA显示。显示画面为“生日快乐”，并且显示有蛋糕图形。生日快乐四个字可在屏幕上进行流动显示。
- 2022-05-30 10:25:57下载
- 积分：1
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DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分：1
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verilog8B10B
8b10b编码方式，verilog语言实现，有测试程序。能成功编码。没有环回验证，读者可自行编写环回验证测试程序。(8b10b encoding, verilog language, test procedures. Successful encoding. No loopback verification, readers can write your own loopback verification test procedures.)
- 2014-04-08 13:37:34下载
- 积分：1
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SystemOfTaxiFeeBasedOnVerilogHDL
摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。
关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分：1
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Fast_median_filter
说明： FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分：1
