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xadc_temperature
说明： 用于FPGA中zynq的温度上报，通过逻辑方式。(It is used to report the temperature of zynq in FPGA by logic)
- 2019-12-18 11:47:43下载
- 积分：1
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costas_PLL
costas载波恢复算法 锁相环路，注释很清楚(costas carrier recovery algorithm PLL)
- 2012-08-03 16:07:41下载
- 积分：1
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FPGA I2C IP
应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the
implementation of custom I2C slave devices. The core provides a means to read and write
up to 256 8-byte registers. These registers can be connected to the users custom logic,
thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used
to set the register address pointer, and write the register data. I2C reads are used to read
the register data. Successive data reads or writes result in data being read or written from
incremental register addresses. There is no limit on how much data can be read or written
in a single access, but the internal register address pointer will wrap round to 0 once it
reaches 255. Note that the address pointer is not initialized at reset, and the address
pointer must
- 2022-05-22 00:28:39下载
- 积分：1
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代码可以实现时隙交换MT89L80芯片功能，完成256x256个时隙交换
使用Verilog编写代码，实现集成芯片MT89L80的功能，代码配置ram后可以直接使用，完成256x256个时隙交换，其中主要模块包括接收模块、发送模块、cpu接口模块，寄存器配置模块，接续寄存器模块等。
- 2022-09-12 20:55:03下载
- 积分：1
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视频测试图形发生器
应用背景关键技术Altera FPGA ；CIII，Cyclone III implemented.16灰度320x240流视频信号发生器。
- 2022-03-05 02:38:57下载
- 积分：1
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轮循机制
" 时间刻度 1ns/1ns
//Round 罗宾没有抢占
模块 roundrb2 （reset_n，赤 角，必需，授予） ；
输入的 reset_n，赤 角 ；
输入 [4:0] 必需 ；
输出 [4:0] 补助金 ；
reg [4:0] 格兰特 = 4"b0000 ；
reg [7:0] 的状态 ；
- 2022-02-03 06:50:42下载
- 积分：1
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shuzizhongsheji
有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)
- 2013-07-18 11:02:24下载
- 积分：1
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interpolation_shaping_filter
内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)
- 2013-11-12 21:13:46下载
- 积分：1
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verilog 多周期CPU设计
计算机组成与设计课程设计
用verilog与FPGA设计多周期CPU
通过modelsim仿真与ISE综合
- 2022-02-28 19:50:26下载
- 积分：1
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crc16_8bit.v
FPGA用于实现crc16编码的verlog源程序，用到的请下载。(FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.)
- 2012-11-08 13:45:14下载
- 积分：1
