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Yoshis_Island_(V1.0)_(U)
Bringing SMW2:YI Back To LIFE Through Rom!
- 2013-01-19 23:40:42下载
- 积分:1
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Verilog教程-夏宇闻
verilog 教程 PPT版本 语法 结构 设计技巧等(Verilog tutorial PPT version)
- 2018-02-26 11:13:55下载
- 积分:1
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IEEE_030_powerworld
The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.
- 2020-07-03 02:20:02下载
- 积分:1
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i2c协议读写寄存器实现
用于进行传感器调试,控制寄存器以及状态寄存器的接口为I2C接口,故做了相应的代码实现,已经做过测试,完成了相关工作,这里不提供测试文件,下载后可以自行测试
- 2022-01-25 15:52:08下载
- 积分:1
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VHDL
先设计序列发生器产生序列:1011010001101010;再设计序列检测器,检测序列发生器产生序列,若检测到信号与预置待测信号相同,则输出“1”,否则输出“0”,并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分:1
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dpwm
数字pwm,用于数字电源控制, 双环控制电压补偿器传输函数同单环控制传输
函数结构相同,只是对应系数不同,因此补偿器结构相同,电流 ADC 采用流水线 ADC,采样数据经过 4 个时钟周期后得到
量化的数字量。电流 ADC 采用流水线 ADC,采样数据经过 4 个时钟周期后得到
量化的数字量。
- 2022-03-25 19:56:57下载
- 积分:1
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VHDL2FSK
VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)
- 2021-05-12 17:30:03下载
- 积分:1
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IOLED
基于单片机显示原理的IO和LED显示原理(Based on the principle of IO chip and LED display shows the principle)
- 2011-09-02 17:09:24下载
- 积分:1
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assg-9-1-(lift-controller)
Lift Controller in vhdl using process statement and state disgram
- 2013-02-28 13:42:28下载
- 积分:1
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chuankou
说明: 本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1