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带同步复位信号的二分频VHDL 程序
带同步复位信号的二分频VHDL 程序-synchronous reset signal with the two-frequency VHDL procedures
- 2022-03-06 12:51:13下载
- 积分:1
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网卡的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.
网卡的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.-NIC
- 2022-03-01 02:33:22下载
- 积分:1
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FPGA的I2S接收模块 audio_in_buff
说明: 用于FPGA的I2S接收模块,仅供学习和参考(audio-i2s receive.use fpga.)
- 2019-04-21 12:11:23下载
- 积分:1
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用于测试ACEX1k30的流水灯程序,晶振频率为20mhz。运行环境Maxplus2...
用于测试ACEX1k30的流水灯程序,晶振频率为20mhz。运行环境Maxplus2-for testing the water ACEX1k30 lights procedures, the frequency of 20MHz crystal oscillator. Operating environment FLEX10K
- 2023-03-02 14:05:03下载
- 积分:1
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pn sequence generator
本设计是一个伪随机数发生器。此设计;
- 2023-02-23 15:45:04下载
- 积分:1
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016_versat_updown_counter
说明: Verilog实现的加减法功能计数器,通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
- 2019-11-27 23:16:27下载
- 积分:1
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sourceinsight的verilog插件
sourceinsight的verilog插件-The Verilog sourceinsight plug-ins
- 2022-02-04 18:20:59下载
- 积分:1
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blif2vhdl格式转换工具
A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).
- 2023-06-13 19:10:02下载
- 积分:1
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paidui
排队电路设计,适用于EDA大作业,大学生适合使用,初学者,仅仅是vhdl的语言,可以借鉴(Queuing circuit design, suitable for EDA operation, college students suitable for use, beginners, only the language of VHDL, can learn from)
- 2017-12-10 23:47:23下载
- 积分:1
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spi
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )
- 2021-04-29 10:58:43下载
- 积分:1