-
freq
vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分：1
-
VHDLcoding
本文件时VHDL的各种编写规范，有助于开发者在平时养成好的编码习惯(This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime)
- 2009-11-20 11:44:58下载
- 积分：1
-
codings
wavelet transform of a signal,it is important and useful code to trans form frequency to time domain
- 2013-11-10 15:10:32下载
- 积分：1
-
-------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is par
---- ----
---- WISHBONE Wishbone_BFM IP Core ----
---- ----
---- This file is part of the Wishbone_BFM project ----
---- http://www.opencores.org/cores/Wishbone_BFM/ ----
---- ----
---- Description ----
---- Implementation of Wishbone_BFM IP core according to ----
---- Wishbone_BFM IP core specification document.---------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is part of the Wishbone_BFM project----
---- http://www.opencores.org/cores/Wishbone_BFM/----
--------
---- Description----
---- Implementation of Wishbone_BFM IP core according to----
---- Wishbone_BFM IP core specification document.
- 2022-05-26 15:36:06下载
- 积分：1
-
本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。...
本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.
- 2023-07-23 01:50:04下载
- 积分：1
-
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-06-13 02:00:08下载
- 积分：1
-
EP1C6_EP1C12核心板原理图，方便自己动手做板学习FPGA
EP1C6_EP1C12核心板原理图，方便自己动手做板学习FPGA-EP1C6_EP1C12 core board schematics, do-it-yourself to do to facilitate learning FPGA board
- 2022-07-11 04:51:07下载
- 积分：1
-
Verilog代码转换到AHB总线APB
verilog code for apb to ahb convert
- 2023-04-27 12:35:03下载
- 积分：1
-
msk_mod_demod
该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)
- 2013-10-14 23:02:39下载
- 积分：1
-
子字节的有效执行
应用背景此文件包括执行与数学计算的子字节。查找表和组合方法已被包括在内。关键技术Xilinx XC3S400 VHDL编程语言已经使用这些代码。
- 2023-05-26 21:50:03下载
- 积分：1
