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Cadence_manual_1.2.pdf
Cadence_manual_1.2.pdf
- 2022-01-26 00:20:48下载
- 积分：1
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74ls138-integral-4-wire-encoder-16
74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)
- 2011-09-20 19:00:59下载
- 积分：1
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moore-FSM
该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)
- 2013-05-10 10:27:09下载
- 积分：1
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Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。...
Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.
- 2022-05-10 23:14:10下载
- 积分：1
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dct
里面含有vhdl和verilog 版本,很好用!dct变换用得很多啊!(Which contains a VHDL and Verilog versions of very good use! Dct transform with a lot ah!)
- 2007-08-27 16:00:31下载
- 积分：1
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daima
Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2014-12-11 20:16:04下载
- 积分：1
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VGA-VHDL-Design
本文件给出了基于VHDL语言的VGA图像显示程序及其工程问件。(This document is presented based on VHDL language VGA image display program and the project asked the pieces.)
- 2010-06-19 11:35:12下载
- 积分：1
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MSK_BER
msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)
- 2020-11-14 11:49:42下载
- 积分：1
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用verilog写的各种实用的分频器，很好的参考例子。
用verilog写的各种实用的分频器，很好的参考例子。-Using Verilog to write a variety of practical divider, a good reference example.
- 2022-10-26 16:30:03下载
- 积分：1
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按键在数字电路设计中经常用到。按键的弹跳现象是数字系统设计中存在的客观问题。按键是机械触点，当接触点断开或闭合时会产生抖动。为使每一次按键只做一次响应，就必须去...
按键在数字电路设计中经常用到。按键的弹跳现象是数字系统设计中存在的客观问题。按键是机械触点，当接触点断开或闭合时会产生抖动。为使每一次按键只做一次响应，就必须去除抖动。本文对按键的抖动信号进行了分析，并通过计数器的方式完成了消除抖动电路模块的设计-?
- 2022-08-07 18:25:32下载
- 积分：1
