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Timing_Closure
详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)
- 2010-08-12 20:02:33下载
- 积分：1
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1
说明： 一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
- 2013-12-24 09:19:13下载
- 积分：1
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test1
利用matlab，对偏振控制器进行仿真，最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)
- 2013-04-07 10:42:15下载
- 积分：1
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8路视频光端机的VHDL源码，此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。...
8路视频光端机的VHDL源码，此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。-8-channel video PDH in VHDL source code
- 2022-07-04 15:14:38下载
- 积分：1
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即使
偶数分频，包括验证程序，verilog实现，可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated
- 2022-04-22 19:15:58下载
- 积分：1
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一种接口控制板的逻辑电路设计CPLD程序。
一种接口控制板的逻辑电路设计CPLD程序。-an interface to the control board CPLD logic circuit design process.
- 2022-06-19 00:18:27下载
- 积分：1
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performance-of-pcie
本白皮书探讨了在PCI Express的因素
技术可能会影响性能。它还
提供指导如何估算
的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)
- 2013-10-29 10:52:43下载
- 积分：1
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FREEDEV数字应用开发板上的I2C总线IP核的verilog描述
FREEDEV数字应用开发板上的I2C总线IP核的verilog描述-FREEDEV digital application development board I2C bus IP core verilog description of
- 2022-03-28 16:58:18下载
- 积分：1
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VHDL example, there are nearly a hundred examples, can be carried out in quartur...
VHDL实例,有近百个实例,都是可以在quarturs 上进行仿真的,大部分都可以通过,对初学者是一非常不错的-VHDL example, there are nearly a hundred examples, can be carried out in quarturs simulation, most of them can pass, for beginners is a very good
- 2022-04-16 23:40:20下载
- 积分：1
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ffirr_166i
fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。
(fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)
- 2012-06-10 17:54:50下载
- 积分：1
