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dpll
用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分：1
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Coding Style
说明： 良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)
- 2020-06-17 12:00:01下载
- 积分：1
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VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料
VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料-VHDL hardware description language and digital logic circuit design, VHDL learning good information
- 2022-11-11 07:30:07下载
- 积分：1
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FIFO
fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)
- 2016-03-16 10:06:12下载
- 积分：1
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HYG32024032T-bT62L-VA
此为华远显示320*240LCD驱动程序，该程序也适用于带RA8806控制器的LCD(This is the Huayuan display 320* 240LCD driver, the program also applies with RA8806 LCD controller)
- 2013-06-08 16:12:53下载
- 积分：1
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ADC实验
基于stm32开发平台的，模拟ad采样程序设计，可直接下载使用(stm32 zhijiexiazaishiyong)
- 2018-02-02 00:32:43下载
- 积分：1
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interr_timer0
interruption routine for PIC16F877
- 2009-12-30 00:43:05下载
- 积分：1
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基于Xilinx FPGA实现PS2键盘鼠标接口。版本1.0
基于Xilinx FPGA实现PS2键盘鼠标接口。版本1.0-Based on Xilinx FPGA realize PS2 keyboard and mouse interface. Version 1.0
- 2022-07-22 17:23:31下载
- 积分：1
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Distributed arithmetic
DA 实现用于 FIR 实现筛选器假定系数固定的那冲激响应和这种行为使得它可能使用的基于 ROM 的下尿路症状
- 2022-07-28 03:52:59下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
