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基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊
基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah
- 2022-03-21 08:29:16下载
- 积分：1
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全加器
利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench(Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language)
- 2018-08-06 14:15:55下载
- 积分：1
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zixiechengxu
用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)
- 2021-04-18 15:28:51下载
- 积分：1
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MAX5250_Serial
对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)
- 2019-06-27 14:19:36下载
- 积分：1
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通信协议AHB_LITE
AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
- 2020-12-15 10:09:14下载
- 积分：1
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从两个小的产生更广泛的ALU
Generating a wider ALU from two small ones
- 2022-07-18 07:53:37下载
- 积分：1
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USB_devide
利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA
中实现U S B 控制器， 并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。(Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.)
- 2007-10-04 16:27:44下载
- 积分：1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分：1
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CH4CH2CH1VHDL 数字电路参考书所有程序5
CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5
- 2022-04-07 20:48:28下载
- 积分：1
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FXY
FPGA做波形发生器，产生8种波形，包括三角波，正弦波，锯齿波，方波等。(FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc.)
- 2019-07-16 16:01:45下载
- 积分：1
