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LAB-9
LAB 9, Excercise for DE2 Altera
- 2014-11-28 11:50:00下载
- 积分：1
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FPGA-a-CPLD-newest-Technology-guide
FPGA／CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA／CPLD为主，详细介绍了FPGA／CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog／VHDL语言，并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例，由浅入深地详述了如何应用FPGA／CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证，读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性，力求通俗易懂。
本书适用于计算机、电子、控制及信息等相关专业的在校大学生，对广大工程技术人员也具有实用价值。(FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value.)
- 2013-08-27 11:39:27下载
- 积分：1
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uart_tx
FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)
- 2015-11-11 13:26:49下载
- 积分：1
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UART串口协议HDL实现，可设波特率、停止位和奇偶校验等
UART串口协议HDL实现，可设波特率、停止位和奇偶校验等。可以在此基础上添加FIFO，以及处理器读写控制等。
- 2022-01-24 10:03:16下载
- 积分：1
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verilog计数器
verilog计数器，属于数字电子技术实验入门的资料。
- 2023-05-18 05:25:04下载
- 积分：1
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dgnszsz
多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分：1
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vey2v585
说明： 该代码实现了俄罗斯方块旋转，左右移动，快速下降，计分和VGA显示等基本功能(This code realizes the basic functions of Russian square rotation, left-right movement, rapid decline, scoring and VGA display.)
- 2020-06-17 19:00:01下载
- 积分：1
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sine-wave-in-UPS
正弦波UPS中的逆变电路 包括原理分析 框图 及原理图(Sine wave UPS inverter circuit the principle analysis block diagram and schematic)
- 2013-03-20 10:13:13下载
- 积分：1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分：1
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BT656_RGB
说明： 将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)
- 2021-03-22 09:29:17下载
- 积分：1
