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一种用于乘数的8x8的制备采用Verilog HDL语言
一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
- 2023-08-11 06:05:03下载
- 积分：1
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verilog HDL编写的出租车计费系统
verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System
- 2022-05-06 06:53:34下载
- 积分：1
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用于fpga学习，共同分享学习经验和交流学习心得
用于fpga学习，共同分享学习经验和交流学习心得-For fpga to learn, to share learning experiences and the exchange of learning
- 2022-02-25 22:21:38下载
- 积分：1
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this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer u...
this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-05-22 09:03:05下载
- 积分：1
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AN66806
提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)
- 2013-08-13 14:42:55下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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n_bit_counter
n bit generic shift registers
- 2011-03-18 17:55:19下载
- 积分：1
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利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024...
利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
- 2022-06-02 16:58:00下载
- 积分：1
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电子手表
在硬件上实现,可以实现一般电子表的功能。比如说计时，显示日期，秒表等功能。还可以显示星期数，可以正常的区分闰年等。并且仿真文件也在其中，反正了其时序变化情况。比较详细。必要出有注释。
- 2022-07-08 11:11:12下载
- 积分：1
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Version1
小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)
- 2013-07-17 11:37:05下载
- 积分：1
