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DDS-Basic-principle
DDS基本原理,详细讲述了DDS基本原理及设计技巧(DDS Basic principle)
- 2015-09-14 21:38:26下载
- 积分:1
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FPGA_SPWM
此代码是由FPGA产生SPWM波的代码,简单易懂(use FPGA to generate SPWM)
- 2019-02-19 16:12:33下载
- 积分:1
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ISE7.1,采用VIRTEX
ISE7.1,采用VIRTEX-II芯片。实现adc数据采样,平均,通道选择,采样时钟选择,数据格式调整,内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
- 2022-03-28 19:34:46下载
- 积分:1
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Polyphase--Filter
多相抽取滤波器。分四相,两倍抽取,采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)
- 2020-09-10 15:58:02下载
- 积分:1
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这是用VHDL实现的8位加法器,对新手有点帮助。
这是用VHDL实现的8位加法器,对新手有点帮助。-This is achieved using VHDL adder 8, a little help to novices.
- 2022-07-20 21:54:41下载
- 积分:1
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gobang
一个用verilog实现的五子棋程序,用在fpga上,连接显示器,可选择与电脑对战或是双人对战,按wsad控制方向,回车控制落子,程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)
- 2015-03-30 13:13:35下载
- 积分:1
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verilog
数字信号除了的FPGA实现的Verilog源代码,之前发过一份是VHDL,各有所需吧,需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
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- 2012-02-25 15:06:35下载
- 积分:1
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VHDL语言100例详解,北京理工大学ASIC研究生出版,这里是1
VHDL语言100例详解,北京理工大学ASIC研究生出版,这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months
- 2022-05-22 16:09:28下载
- 积分:1
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FSK
2FSK的matlab仿真,叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分:1
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chaotic_1d
说明: 一维超混沌随机数的生成verilg,还有testbench仿真激励,modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)
- 2020-05-11 12:45:42下载
- 积分:1