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adaptive
这是基于MATLAB编程实现自适应滤波器，并在XILINX的FPGA上硬件可实现的模型文件(This is based on the MATLAB programming adaptive filter, and the XILINX' s FPGA hardware can be a model document)
- 2009-06-24 13:26:32下载
- 积分：1
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clk
sin波形发生图形，应用智能老师款到即发了快速打击 (sin waveform generation graphics application smart teacher paragraph to that made a rapid strike)
- 2013-02-24 15:46:58下载
- 积分：1
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pll_carrier_syn
本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)
- 2013-04-11 09:18:49下载
- 积分：1
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zybo 音频播放
zybo audio 音频播放，可以实现在pc端播放音乐然后在zybo上放出来，通过改变寄存器也可以从麦克风上我们自己说话然后通过音频口放出来
- 2022-07-04 17:15:15下载
- 积分：1
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Decodificador
System Verilog decodificator.
Enters a value(binary), drops hundreds, tens and units in BCD
- 2013-05-15 02:11:45下载
- 积分：1
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MD5
哈希算法FPGA实现代码，采用MD5算法，并给出了仿真波形。(MD5 hashing algorithm for FPGA implementation code)
- 2020-07-03 00:40:02下载
- 积分：1
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uart2spi-master
说明： this code works with spi and uart interfaces.
- 2020-07-21 21:10:59下载
- 积分：1
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SinglePeriodCPU
说明： verilog语言书写，单周期CPU源码(single period CPU)
- 2020-11-25 11:59:32下载
- 积分：1
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AHB_SMSS
ahb single master single slave rtl design
- 2021-04-21 11:28:49下载
- 积分：1
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中值滤波算法
中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法，搭建出完整的数据处理系统架构，通过仿真和验证来判断数据的处理效果，并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)
- 2018-05-30 13:44:03下载
- 积分：1
