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verilog program for iic bus design. the pakege includes iic protocl master progr...
Verilog数字系统设计教程【夏宇闻】原书第十章:IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
- 2022-01-31 13:13:45下载
- 积分:1
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cputimer
基于 CPU 的精确计时器,时钟频率越高,计时越准(Based on the exact CPU timer, the higher clock frequency, the more time-quasi-)
- 2009-04-25 10:36:11下载
- 积分:1
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MIPSTOP
misp顶层文件,verilog实现misp架构,并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分:1
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codic
8级cordic 算法verilog (8 cordic algorithm verilog)
- 2013-08-21 11:31:46下载
- 积分:1
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FIRVerilogHDL
it is a fir filter program VerilogHDL.(it is a filter program VerilogHDL fir.)
- 2007-04-12 22:21:26下载
- 积分:1
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这是一个在FPGA上实现CRC算法的程序,包含了CRC
这是一个在FPGA上实现CRC算法的程序,包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
- 2022-12-18 23:05:03下载
- 积分:1
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FPGA
基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source
- 2022-05-30 01:45:47下载
- 积分:1
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EDA1_MusicCalculator
音乐计算器,可实现999以下加减法及与非运算功能,并能够播放两段音乐,可下载到FPGA板子上实现。(Music Calculator)
- 2020-08-16 23:38:25下载
- 积分:1
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FSM_Robustness_Testing
基于有限状态机的健壮性测试研究。
关键词:健壮性测试;增强有限状态机;全球平台;安全通道协议(The Research of Robustness Testing Based on FSM)
- 2012-09-06 14:08:56下载
- 积分:1
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M_M
此为数学形态滤波器消燥的代码,用于一维信号,涉及一个具体的例子,需要的话可以自己修改,修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)
- 2013-08-29 21:36:37下载
- 积分:1