-
DES加密算法的VHDL实现,采用流水线技术实现
DES加密算法的VHDL实现,采用流水线技术实现(The VHDL implement of DES encrypt algorithmic)
- 2020-07-01 03:00:02下载
- 积分:1
-
基于fpga和xinlinx ise的音乐播放器vhdl程序,希望对你有所帮助!...
基于fpga和xinlinx ise的音乐播放器vhdl程序,希望对你有所帮助!-and xinlinx ideally music player VHDL process, and I hope to help you!
- 2023-02-07 05:35:03下载
- 积分:1
-
RS_5_3_CODEC
完成RS(5,3)编码程序,运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)
- 2010-05-25 21:21:34下载
- 积分:1
-
QAM
OFDM中的16QAM星座映射的实现实现详细代码(In OFDM 16QAM constellation mapping to achieve the realization detailed code)
- 2021-03-11 17:59:25下载
- 积分:1
-
cnv_enc_modify
卷积码(2,1,7)编码器,一个输入,两个输出(Convolution code (2,1,7) encoder, an input and two outputs)
- 2015-05-20 10:21:56下载
- 积分:1
-
sd_models_verilog
测试过可用的SD仿真模型,VERILOG语言(SD card simulation modle, test OK)
- 2021-02-26 20:09:37下载
- 积分:1
-
RS
说明: 本文设计了基于FPGA的,用verilog HDL语言描述的在伽罗华域GF( )上的RS(6,4)编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述,然后在软件上进行编译、仿真,最终实现RS(6,4)编码,下载之后用chipscope采集数据,分析符合仿真结果,达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)
- 2017-08-25 17:59:14下载
- 积分:1
-
RISC
说明: RISC全部源码,包含仿真文件,使用makefile脚本编写,能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)
- 2020-04-14 22:10:52下载
- 积分:1
-
FPGA
基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source
- 2022-05-30 01:45:47下载
- 积分:1
-
SPWM
FPGA上用verilog写的SPWM控制程序,完美运行!自由调试,毕设内容,十分宝贵(The SPWM control program by verilog FPGA perfect run! Free commissioning, Bi-based content, invaluable)
- 2013-05-05 21:36:10下载
- 积分:1