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首页 » VHDL » USB1.1 IP核心控制设备,用硬件描述语言…

USB1.1 IP核心控制设备,用硬件描述语言…

于 2022-01-30 发布 文件大小:128.67 kB
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代码说明:

usb1.1的设备控制器IP核,是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.

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