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硬件仿真
说明： 基于FPGA的QPSK系统仿真及验证，硬件部分。(Simulation and verification of QPSK system based on FPGA)
- 2021-02-06 16:21:17下载
- 积分：1
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"Verilog HDL Design Guide" 4
《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4
- 2023-06-21 01:20:03下载
- 积分：1
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FPGA数字AGC(帮同学做的毕业设计)
FPGA数字AGC(帮同学做的毕业设计)-FPGA digital AGC (help students to do the graduation project)
- 2022-03-17 18:29:50下载
- 积分：1
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Static RAM is a tube composed of MOS flip
静态RAM是由MOS管组成的触发器电路，每个触发器可以存放1位信息。只要不掉电，所储存的信息就不会丢失。因此，静态RAM工作稳定，不要外加刷新新电路，使用方便。但一般SRAM的每一个触发器是由6个晶体管组成，SRAM芯片的集成度不会太高，目前较常用的有6116（2K×8位），6264（8K×8位）和62256（32K×8位）。6264RAM有8192个存储单元，每个单元为8位字长。-Static RAM is a tube composed of MOS flip-flop circuit, each flip-flop can store one message. Long as it does not brown-out, the stored information will not be lost. Therefore, the static stability in the work RAM, do not refresh plus the new circuit and easy to use. But generally each SRAM trigger is composed of six transistors, SRAM chip integration will not be too high, there are currently more commonly used 6116 (2K × 8 bit), 6264 (8K × 8 bit) and 62256 (32K × 8 bits). 6264RAM have 8192 storage units, each for 8-bit word length.
- 2022-04-10 07:00:36下载
- 积分：1
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build synthesizer on a de2 dev fpga board
build synthesizer on a de2 dev fpga board
- 2023-07-24 00:25:04下载
- 积分：1
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基于vhdl的PWM发生器
基于vhdl的PWM发生器-VHDL-based PWM generator
- 2022-03-04 15:27:12下载
- 积分：1
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cpu-maxplus
MaxplusII编写的简易cpu，可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)
- 2007-06-08 17:55:10下载
- 积分：1
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divider
verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)
- 2011-08-29 09:12:21下载
- 积分：1
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VHDL实现的8位乘法器，所有仿真全部通过
VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier
- 2022-01-24 12:51:20下载
- 积分：1
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leading-zero
对于32位寄存器前导零个数的计数，一个简单的程序(32 registers a leading zero number of counts, a simple procedure)
- 2012-06-05 16:41:11下载
- 积分：1
