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FPGAVHDL
vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)
- 2020-12-17 12:19:13下载
- 积分：1
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cm03pr2
In computer storage, multipath I/O is a fault-tolerance and performance enhancement technique whereby there is more than one physical path between the CPU in a computer system and its mass storage devices through the buses, controllers, switches, and bridge devices connecting them
- 2013-06-09 00:41:09下载
- 积分：1
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基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样...
基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样-based on the fpga and fskpsk signal generator,can achieve sample to the 1.2kHz and 2.4kHz sin wave
- 2023-08-25 08:15:03下载
- 积分：1
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一位LED显示的VHDL程序，挺简单的，买的开发板里面带的
一位LED显示的VHDL程序，挺简单的，买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone
- 2023-07-18 00:45:02下载
- 积分：1
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clock_seg
用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)
- 2013-05-20 13:53:06下载
- 积分：1
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HDLC some relevant documents, HDLC design may be very helpful!
HDLC的一些相关文档，可能对HDLC设计有很大的帮助！-HDLC some relevant documents, HDLC design may be very helpful!
- 2022-10-21 11:55:03下载
- 积分：1
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lab_instructions3
The objective of the labs today is to give you a basic understanding of FPGA design and
enough experience to begin your own FPGA design with the ISE 10.1 tools and the
Xilinx Spartan-3A DSP 1800A Starter Kit.
- 2010-12-31 17:16:42下载
- 积分：1
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lcd verilog hdl 源码 可以直接使用，适用modelsim
lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source
- 2023-03-09 05:25:03下载
- 积分：1
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contract
it is a filter contract VHDL .(it is a filter contract VHDL.)
- 2007-04-12 22:27:23下载
- 积分：1
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ASKMod
ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)
- 2017-04-17 10:46:19下载
- 积分：1
