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An_enhanced_security_measures_DSP
通过总结当前对处理器架构的安全性能的处理方法，提出一种增强DSP处理器安全性能的方法。主要从并行性方面进行了改进。最后对改进的方法进行了仿真和结果分析。(By summing up the current security architecture of the processor performance approach, a DSP processor to enhance the safety performance of the method. Mainly from the aspects of parallelism to improve. Finally, improved methods and results of simulation analysis.)
- 2009-03-30 11:18:09下载
- 积分：1
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fpga_dsp_simple
dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
- 2013-04-14 15:17:20下载
- 积分：1
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performance with rayleigh
matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分：1
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1_ADDER
说明： 第1例到第6例的源描述都是从第8例的程序包中
提取出来的,不能单独编译,这些例子的编译与
模拟请参考第8例.(Example No. 1 to the first six cases are the source described in Example 8 from the first package to extract it and can not be a separate compiler, which compiler and simulation examples please refer to the first eight cases.)
- 2008-09-09 18:00:16下载
- 积分：1
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2010_5
PI控制器的算法及源码，迅速掌握FPGA的VHDL算法实现！(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)
- 2014-07-04 15:25:59下载
- 积分：1
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DDR3_user_design
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)
- 2012-02-02 15:16:00下载
- 积分：1
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HASH
hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )
- 2015-01-29 18:48:13下载
- 积分：1
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- 2023-02-07 15:40:03下载
- 积分：1
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Timing1111_Symcronization
使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)
- 2021-05-07 14:28:36下载
- 积分：1
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ad9288
使用FPGA控制AD9288，方便移植，可以拿来直接使用，适合新手学习(Use FPGA control AD9288, easy migration, can be used to directly use for novices to learn)
- 2021-04-21 08:58:49下载
- 积分：1
