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dingshi
定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分：1
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High
高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard
- 2022-07-18 13:13:37下载
- 积分：1
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picoblaze实现串口通信...难道一定要20个字吗?
picoblaze实现串口通信...难道一定要20个字吗?-implement uart communication base on picoblaze
- 2022-03-31 20:43:55下载
- 积分：1
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sonic
基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)
- 2015-04-27 15:41:19下载
- 积分：1
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手机号码归属地查询,代码详尽，简单易懂，欢迎使用！
手机号码归属地查询,代码详尽，简单易懂，欢迎使用！-hello!welcome to my code !thank you !
- 2022-01-27 16:05:17下载
- 积分：1
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car
基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器(Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors)
- 2015-03-21 18:06:18下载
- 积分：1
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tuoji_fpga(xp2_8)_v2
特大好消息，这是LED全彩控制卡的FPGA的源程序，做LED开发的，绝对有很好的价值(Big good news, this is full-color LED control card FPGA of the source, do LED development, the absolute value of good)
- 2010-07-19 16:18:27下载
- 积分：1
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multi8x8
节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)
- 2006-12-07 13:22:48下载
- 积分：1
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verilog program for iic bus design. the pakege includes iic protocl master progr...
Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
- 2022-01-31 13:13:45下载
- 积分：1
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SPWM_FPGA
用FPGA实现SPWM波输出，其中包含三角波和正弦波(With the FPGA realization of SPWM wave output, including triangle wave and sine wave
)
- 2015-04-19 11:24:18下载
- 积分：1
