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jtag
verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)
- 2021-04-27 14:18:44下载
- 积分：1
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DE2_115_SD_Card_Audio_Player
该代码实现了对SD 卡的读写操作，是一个较好的范例。(The code achieves access reading SD CARD based on DE-2，It is
a good example。)
- 2012-08-14 00:29:47下载
- 积分：1
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OFDM_802_11
ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。(Source code of transmission link and reception link of OFDM)
- 2020-12-22 21:19:06下载
- 积分：1
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dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2022-06-20 23:49:32下载
- 积分：1
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UART0407
ise平台模拟UART，并与PC机实现收发（+1）(ISE platform simulation UART and transceiver.)
- 2013-04-22 15:38:36下载
- 积分：1
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verilog hdl verilog hdl verilog hdl
verilog hdl verilog hdl verilog hdl-verilog hdl
- 2022-02-09 22:11:06下载
- 积分：1
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2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES...
2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH" s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-07-17 15:40:45下载
- 积分：1
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comp
The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
- 2012-06-05 23:16:25下载
- 积分：1
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Idddc_30mF
中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号
(IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)
- 2012-07-25 23:56:30下载
- 积分：1
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ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分：1
