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BoneMicoren
Bone microphnoe simulator.
this is a trial to de-noise the bone microphone signals.
This also utilizes om-lsa algorithm
- 2012-12-12 04:47:28下载
- 积分：1
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n_bit_counter
n bit generic shift registers
- 2011-03-18 17:55:19下载
- 积分：1
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verilog hdl verilog hdl verilog hdl
verilog hdl verilog hdl verilog hdl-verilog hdl
- 2022-07-23 23:39:39下载
- 积分：1
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DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme
DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
- 2022-02-25 20:23:26下载
- 积分：1
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ds190-Zynq-7000-Overview
zedboard的资料说明书，可以帮助你理解(zedboard data sheets, can help you understand)
- 2012-11-06 10:51:14下载
- 积分：1
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sopc
基于FPGA的SD卡音频播放器
经过调试可以直接用，音质很好有MP3的所有功能(FPGA-based audio player, SD card can be directly used after debugging, good sound quality with all the features of MP3)
- 2021-01-02 23:08:57下载
- 积分：1
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ModelSim_
FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)
- 2013-07-24 19:20:57下载
- 积分：1
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hang_us14
Synthetic Aperture Radar (SAR) imaging simulation target, Using wavelet denoising thought, LCMV optimization design array signal processing.
- 2020-08-25 20:58:14下载
- 积分：1
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计算机组成原理课程设计(vhdl语言实现)
1. 一位全加器设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY add IS
PORT(a,b,cin:IN STD_LOGIC;
Co,S:OUT STD_LOGIC);
END ENTITY add;
ARCHITECTURE fc1 OF add is
BEGIN
S
- 2023-06-03 00:55:02下载
- 积分：1
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2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES...
2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH" s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-07-17 15:40:45下载
- 积分：1
