登录
首页 » VHDL » 检测上升沿的verilog程序,有验证程序,可用synplify验证

检测上升沿的verilog程序,有验证程序,可用synplify验证

于 2022-01-31 发布 文件大小:1,006.00 B
0 88
下载积分: 2 下载次数: 1

代码说明:

检测上升沿的verilog程序,有验证程序,可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 基于FPGA的电子时钟设计
    具体设计内容计时功能:电子表的基本功能,要求用LCD显示,显示格式是时、分、秒;校时功能:用户可以更改当前时间。设置闹钟时间:用户可以设置闹钟时间,其操作过程与校时过程一样;整点报时开关:整点报时可以由用户设定为开启或关闭两种状态,当整点报时开启时,电子表会在整点时发出1秒的闹铃声(在UP3的板上用一个LED表示);闹钟功能开关:闹钟由用户设定为开启或关闭,当闹钟开关开启时,如果当前时间与设置的闹钟时间一致,发出长达10秒的闹铃声;
    2022-11-29 04:25:04下载
    积分:1
  • Documentation Of Digital Electronic Systems With VHDL from US DOD.
    Documentation Of Digital Electronic Systems With VHDL from US DOD.
    2022-05-09 12:50:24下载
    积分:1
  • VHDL language used to achieve 8
    用VHDL语言实现8-3线编码器,16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder
    2023-08-20 10:35:02下载
    积分:1
  • mp3codec
    it is used to compile codec
    2009-03-04 17:00:53下载
    积分:1
  • AES128
    AES128 encription vhdl code
    2014-03-05 00:48:13下载
    积分:1
  • ABencode
    FPGA实现增量式光栅尺正交脉冲解码,基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)
    2020-11-21 20:59:36下载
    积分:1
  • 本设计是针对LEON3 Altera Nios II startix2
    This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the
    2022-05-18 19:00:04下载
    积分:1
  • LMS_Matlab
    LMS算法自适应滤波器的Matlab仿真分析.(LMS matlab fangzhenchengxu.)
    2011-07-06 12:43:26下载
    积分:1
  • Verilog入门
    verilog的入门级别的例子(转载)-Verilog entry-level examples (reproduced)
    2022-06-20 04:33:09下载
    积分:1
  • aetgdffh tghj tjfgj FDG VBN T
    4weimimasuo 可运行 可仿真 -aetgdffh tghj tjfgj fdg vbn t
    2022-08-16 19:53:03下载
    积分:1
  • 696518资源总数
  • 105549会员总数
  • 12今日下载