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Quartus在自己写的TCL,分布IO的例子。
quartus 中,自己写的tcl,分配io的例子。-Quartus in their own writing tcl, distribution io example.
- 2022-03-24 02:15:21下载
- 积分:1
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spi_2
说明: DAC3283 寄存器初始化,SPI驱动(Dac3283 register initialization, SPI drive)
- 2020-03-14 09:56:50下载
- 积分:1
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cpu
说明: 一个简单的CPU设计,支持add,sub,mvi,mv四条指令,用Verilog语言编写,在Quratus II上编译通过,仿真正确。(A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.)
- 2011-04-09 12:22:09下载
- 积分:1
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hidejj
实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
- 2017-08-02 14:23:12下载
- 积分:1
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tdma_code
tdma参数化模块。可以自动生成2的n次的tdma哥时隙,用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)
- 2013-09-03 21:52:51下载
- 积分:1
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Xilinx公司Accel DSP项目
xilinx accel dsp实例项目工程-xilinx accel dsp project
- 2023-03-09 20:10:02下载
- 积分:1
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dds_ok1
说明: 基于FPGA的信号发生器,产生了正弦波,方波,锯齿波和三角波四种波形,按下一次按钮,波形切换一次。按下另一个按钮,改变波形的频率(The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform)
- 2020-09-16 18:30:37下载
- 积分:1
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cordic
cordic算法,实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)
- 2020-06-29 14:00:01下载
- 积分:1
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如果不考虑占空比,直接利用计数器来进行分频,则占空比会发生变化。下面程序实现1:1的三分频。...
如果不考虑占空比,直接利用计数器来进行分频,则占空比会发生变化。下面程序实现1:1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
- 2022-01-21 05:34:37下载
- 积分:1
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texi
基于FPGA的出租车计价器,欢迎大死同学多多交流(FPGA-based Taximeter, welcomes the dead students more exchanges)
- 2008-05-09 22:49:48下载
- 积分:1