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数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法...
数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different sub-frequency ratio, NC prescaler value can be used include parallel preset counter adder design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.
- 2023-04-20 16:25:03下载
- 积分：1
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数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端...
数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。
-NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.
- 2022-04-28 17:05:55下载
- 积分：1
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reversible-squarer
it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
- 2015-04-21 15:05:54下载
- 积分：1
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FFT_64points
64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)
- 2021-04-03 11:29:07下载
- 积分：1
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C-V2X-master
LTE is an abbreviation for Long Term Evolution.
- 2019-06-29 01:08:09下载
- 积分：1
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MCU and FPGA communication functions: SCM control FPGA to write a byte of data...
单片机与ＦＰＧＡ的通信
功能 :单片机控制写FPGA一字节数据
单片机控制写FPGA一字节数据时钟 (注意读写数据端口可复用,也可分用)
单片机控制发送数据端口
-MCU and FPGA communication functions: SCM control FPGA to write a byte of data SCM control FPGA to write a byte of data clock (Note that the read and write data ports can be re-used, but also can be divided into use) SCM control to send data port
- 2023-04-21 07:05:03下载
- 积分：1
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FM radio decoder and controller VHDL, Xilinx provide. I thank other.
FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
- 2022-10-05 04:50:03下载
- 积分：1
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Using-fpga-implementation-SDI
用fpga实现SDI（ xapp1014-xilinx-sdi）赛灵思原厂资料(Using fpga implementation SDI (xapp1014-xilinx-sdi) Xilinx original data)
- 2013-10-29 15:02:18下载
- 积分：1
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FPGAshixu
FPGA经验总结：时序是设计出来的
我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)
- 2015-03-13 10:27:51下载
- 积分：1
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integrator
this code for integrator for 8 bit signal
- 2010-01-07 16:06:04下载
- 积分：1
