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DCT
用verilog语言实现DCT编解码
附有DCT的说明(Using Verilog language realize DCT codec with a description of DCT)
- 2020-11-14 15:19:41下载
- 积分：1
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Constant_PQ_Microgid_matlab
逆变器并网发电的主要是逆变器输出正弦波电流的控制技术，要求与电网同频同相的电流，此matlab模型中使用锁相环技术，恒功率控制，LCL滤波器技术使达到并网要求(Constant_PQ_Microgid )
- 2021-04-02 10:09:07下载
- 积分：1
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dac5686
在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)
- 2014-09-11 11:05:20下载
- 积分：1
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Controller RAM read and write, using verilog implementation of easy
RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
- 2022-02-09 14:58:27下载
- 积分：1
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sinwave
使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results
)
- 2013-09-18 15:27:27下载
- 积分：1
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设计含异步清零和同步时钟使能的加法计数器
设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter
- 2023-03-27 21:05:03下载
- 积分：1
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ADC_Data_Recv_Module
接收机测试输入信号，
生成正余弦波，采样率、频率、幅度、相位可调节
并将生成的数据进行输出
压缩包包括Verilog代码、testbench代码、word文档
matlab仿真代码(The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code)
- 2017-12-08 17:56:02下载
- 积分：1
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8253
8253可编程定时器/计数器芯片 VeriLog实现(8253 programmable timer/counter chip VeriLog achieve)
- 2013-05-31 20:40:23下载
- 积分：1
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EMIF
EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)
- 2020-12-04 10:39:24下载
- 积分：1
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页面置换算法中的三种算法相关程序代码
FIFO LUR OPT
页面置换算法中的三种算法相关程序代码
FIFO LUR OPT-yemianzhihuansuanfa
- 2022-10-19 08:10:03下载
- 积分：1
