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篮球24秒可控计时器设计
用VHDL语言设计篮球24秒可控计时器功能说明：1.具有24秒计时、显示功能； 2.设置外部按键，完成清零、暂停、恢复控制； 3.24秒倒计时，时间间隔为1s； 4.时间到后发出报警信号，并在3s后解除。
- 2022-05-28 22:06:17下载
- 积分：1
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这是一个FPGA sparttan 3E基础工程，
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.
- 2022-11-15 01:50:04下载
- 积分：1
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yuanchengxu
基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)
- 2011-11-19 13:36:54下载
- 积分：1
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T8051
IT8051，增强版的T51，兼容DW8051核的多数端口，IO需要扩展后使用
- 2022-02-12 17:39:36下载
- 积分：1
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DE2 development company for the altera board SD_Card_Audio examples
用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
- 2022-12-25 12:55:03下载
- 积分：1
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EEPROM
控制器灯具有线和无线控制器采用STC11F02做的(Controller for lamp wired and wireless controller using STC11F02 to do)
- 2012-01-05 14:45:10下载
- 积分：1
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muxcounter
Multiplexer styles in VHDL
- 2017-09-11 14:06:42下载
- 积分：1
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basic_dff
spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)
- 2012-04-23 16:40:17下载
- 积分：1
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HASH
hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )
- 2015-01-29 18:48:13下载
- 积分：1
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Cadence VHDL Operational the package, seeking to achieve root, You are not squar...
Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
- 2022-08-16 03:35:39下载
- 积分：1
