-
数字电子设备上下计数器的实现
上/下计数器是有用的大规模集成
- 2022-01-26 01:21:27下载
- 积分：1
-
SMII 到 MII 转换的VHDL代码
SMII 到 MII 转换的VHDL代码-SMII to MII conversion of VHDL code
- 2023-06-26 06:15:03下载
- 积分：1
-
within waveform generator, Adder, classic dual
内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
- 2023-09-02 09:40:03下载
- 积分：1
-
4BITMUIT
利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)
- 2013-09-05 10:06:52下载
- 积分：1
-
fujieqi
在这里设计的是时分复用系统，就是要将三路8比特数据复用到同一信道上进行传输(Here is the design of time division multiplexing system, is to take the road three 8 bit data multiplexed onto the same channel for transmission)
- 2014-10-16 09:31:25下载
- 积分：1
-
kbfp
实现任意整数倍的信号分频，可调，不存在毛刺，波形完整，可运于信号的分析与检测(Arbitrary integer multiple of the signal frequency, adjustable, there is no glitch, waveform integrity, and can transport the analysis and the detection signal)
- 2015-08-14 22:58:22下载
- 积分：1
-
FPGAPDSCDMA
上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)
- 2013-02-10 14:31:46下载
- 积分：1
-
vgachar
VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)
- 2012-05-31 10:35:14下载
- 积分：1
-
Altera-LVDS_IP
自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
- 2020-12-16 14:39:13下载
- 积分：1
-
Verilog HDL 135例指南：Verilog HDL语言类似于C语言，以…
verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6
- 2022-09-27 03:05:03下载
- 积分：1
