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自适应滤波器
由于衍射、散射、反射和稀疏等环境损伤的增加,其后果是信号视线的丧失和干扰。自适应信号处理可以克服这些缺陷。该代码是用甚高速硬件描述语言(VHDL)编写的,用以滤除高频,减少噪声和干扰。
- 2023-07-04 11:00:03下载
- 积分:1
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VHDL design language based on 8
基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples
- 2023-06-06 01:10:04下载
- 积分:1
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vhdl,序列信号发生器,发出11101010,可更改为任意序列
vhdl,序列信号发生器,发出11101010,可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of
- 2023-08-12 03:05:03下载
- 积分:1
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Multiplier
A multiplier unit in VHDL
- 2010-01-05 11:42:02下载
- 积分:1
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这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用...
这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
- 2022-05-22 23:36:04下载
- 积分:1
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FSK
2FSK的matlab仿真,叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分:1
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stopwatch-based-on-VHDL
基于VHDL的电子秒表的设计,使用VHDL语言描述一个秒表电路,利用QuantusII软件进行源程序设计,编译,仿真,最后形成下载文件下载至装有FPGA芯片的实验箱,进行硬件测试,要求实现秒表功能。(Design of electronic stopwatch based on VHDL)
- 2013-11-27 15:42:41下载
- 积分:1
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alu3
用verilog语言编写,一个8-bit ALU,可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)
- 2008-05-12 12:48:49下载
- 积分:1
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ofdm_modulation
OFDM modulation source code written in Matlab
- 2009-06-01 17:52:44下载
- 积分:1
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emmc_cmd_interface_module
emmc控制芯片CMD命令线主机接口模块,(emmc control chip CMD command line host interface module)
- 2021-02-09 11:19:53下载
- 积分:1