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recarry
fir filter 程序
老师上课留的作业，在这里跟大家分享一下，希望能有所帮助(fir filter procedures teacher in the class to stay the operation here to share with you, hope can be helped)
- 2006-10-11 19:34:43下载
- 积分：1
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VGA字符显示VHDL程序
可以直接用于工程的设计与开发
VGA字符显示VHDL程序
可以直接用于工程的设计与开发-VGA display characters can be directly used for VHDL design and development
- 2022-01-24 18:21:47下载
- 积分：1
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扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现
扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram
- 2023-08-17 13:20:04下载
- 积分：1
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VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分：1
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Static RAM is a tube composed of MOS flip
静态RAM是由MOS管组成的触发器电路，每个触发器可以存放1位信息。只要不掉电，所储存的信息就不会丢失。因此，静态RAM工作稳定，不要外加刷新新电路，使用方便。但一般SRAM的每一个触发器是由6个晶体管组成，SRAM芯片的集成度不会太高，目前较常用的有6116（2K×8位），6264（8K×8位）和62256（32K×8位）。6264RAM有8192个存储单元，每个单元为8位字长。-Static RAM is a tube composed of MOS flip-flop circuit, each flip-flop can store one message. Long as it does not brown-out, the stored information will not be lost. Therefore, the static stability in the work RAM, do not refresh plus the new circuit and easy to use. But generally each SRAM trigger is composed of six transistors, SRAM chip integration will not be too high, there are currently more commonly used 6116 (2K × 8 bit), 6264 (8K × 8 bit) and 62256 (32K × 8 bits). 6264RAM have 8192 storage units, each for 8-bit word length.
- 2022-04-10 07:00:36下载
- 积分：1
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这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面
这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
- 2022-02-06 13:26:07下载
- 积分：1
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基于IIC的EEPROM模型代码
说明： 基于IIC协议的EEPROM模型，可实现串行数据转并行数据，并行数据转串行数据，分为EEPROM模块，EEPROM_WR模块，signal模块，Top模块(The EEPROM model based on IIC protocol can convert serial data to parallel data and parallel data to serial data. It is divided into EEPROM module and EEPROM module_ WR module, signal module, top module)
- 2020-10-02 00:30:24下载
- 积分：1
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本例为TLC7524接口电路VHDL原程序
本例为TLC7524接口电路VHDL原程序-Example for the TLC7524 interface circuit VHDL original procedure
- 2022-03-01 05:38:08下载
- 积分：1
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Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
Qutuas II v7.1的key_gen 对sp1无效
这就是个v7.1 sp1的key_gen
-Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
- 2023-07-28 18:25:02下载
- 积分：1
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简单的键盘接口模块程序
一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分：1
